Altera_Forum
Honored Contributor
15 years agoStratix IV GX - QDR w/ Uniphy
I have a custom board with two x18 250MHz QDRs (GS8662D18E-250I). I am using the example project to test each QDR individually. One of the QDRs passes all the tests from the example driver while the other always fails. I do not have any trouble getting through calibration and the echo clock, as measured at the QDR looks good.
I did run the pin_assignments.tcl and timequest reports 0 failures. I modified the example driver to only write 1's and a typical failure is shown in the attached screenshot. This should be a burst of 4 so it is as if the last x18 stage is not getting clocked in correctly. Any thoughts as to what might be causing this? What can I do to correct this?