Stratix IV GX - QDR w/ Uniphy

I'm suspecting it has to do with the postamble timing. From the external memory interface handbook: Volume 4 Section III Debugging.

Postamble Timing Issues and Margin

The postamble timing is set by the PHY during calibration. You can diagnose

postamble issues by viewing the pnf_per_byte signal from the example driver.

Postamble timing issues mean only read data is corrupted during the last beat of any read request.

That is the only information that it provides on the topic. How would one make adjustments to correct this?