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dncmrc1's avatar
dncmrc1
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
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Stratix 10 Transceiver PHY bonding and multiple TX PLL clock inputs (for DisplayPort TX)

We are using a Stratix 10 L-Tile/H-Tile Transceiver Native PHY to implement a DisplayPort TX and RX. The transceiver is set as Basic (Enhanced PCS), TX/RX Duplex. The TX PMA is set as Non bonded, wi...
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  • CheepinC_altera's avatar
    CheepinC_altera
    5 months ago

    Hi,

     

    After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP.

     

    Please let me know if you have any questions or concerns. Thank you.

dncmrc1's avatar
dncmrc1
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Hi,

It looks like bonding is not supported at rates > 17.4G:

Also the ATX PLL refuses to configure for 20G with bonding:

Can you please help?

Regards

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi,

 

After consulting with our DisplayPort (DP) IP experts, it appears that our DP is currently not operating in bonded mode for multi‑lane support. You may want to explore our DP IP.

 

Please let me know if you have any questions or concerns. Thank you.