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HBhat2's avatar
HBhat2
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5 years ago

Stratix 10 Native PHY PMA register details for reverse serial loopback

Hi, Board: Stratix 10 SoC Kit- L-tile. I am accessing PMA registers to configure the transceiver pairs (GXT) in reverse serial loopback mode. As per the transceiver user guide: {0x11D[0], 0...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi HPB ,


Based on user guide doc table A.4.4 - Loopback setting table :

  • Encodings {0x11D[0], 0x132[5:4],0x137[7], 0x144[1], 0x142[4]}
  • 6'b000000 - Disable reverse serial loopback
  • 6'b100101 - Enable pre-CDR reverse serial loopback
  • 6'b001010 - Enable post-CDR reverse serial loopback


However, there is also separate note on page 393 that mentioned GXT channel doesn't support reverse serial loopback as well


Therefore, don't try it on GXT channel else it may end up with weird result as seen by you.


Thanks.


Regards,

dlim


HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi dlim,

I am aware of reverse serial loopback not supported in GXT speed (More than 17Gbps).

What I mentioned previously is the transceiver channel whichever I am using is GXT capable (In L-tile all channels can not support upto 26Gbps). But, the channels are configured @10.3125Gbps rate.

With Regards,

HPB