Stratix 10 Dual-Port RAM (with 2 clocks) generation problem

Hi,

i'm converting my Stratix V design to Stratix 10.

in Stratix V i used the MegaWizard in quartus (13.1 i think) to create an SRAM with:

• 2 read+write ports
• 512 rows of 128bits each (same data bus width on both ports)
• different clock for each of the ports
• byte_enable support on both ports

using QuarusPro "IP Catalog" i tried to get the same SRAM functionality.

i used the "memory user guide" from Intels website

at section 4.1.3. RAM: 2-PORT Intel FPGA IP Parameters

In the optional clocking schemes for the generated SRAM.

There is an option for different clocks for the 2 ports (A & B)

When I try to generate the SRAM in the IP Catalog. I configure the parameters as follows :

Then

And then

When coming to select the clocking scheme, I do not see the suggested option by the DOC.

If selecting "Customize clocks for A and B ports"

I can not use byte_enable on the ports

please advise.

Best Regards,

Amir Nassie