Amir_Nassie
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New ContributorStratix 10 Dual-Port RAM (with 2 clocks) generation problem
Hi, i'm converting my Stratix V design to Stratix 10. in Stratix V i used the MegaWizard in quartus (13.1 i think) to create an SRAM with: 2 read+write ports 512 rows of 128bits each (same data ...
Hi,
If you look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf Table 10, it will shows that Stratix 10 does not support True Dual Port with byte enable features.
