Forum Discussion
New ContributorStratix 10 Dual-Port RAM (with 2 clocks) generation problem
Hi,
If you look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf Table 10, it will shows that Stratix 10 does not support True Dual Port with byte enable features.
Super ContributorI think there's a disconnect between the documentation and the parameter editor. I believe that the "Customize" option is what you need to select, but are you saying that when you do that, the byte_enable options for the two ports that you show in your last screenshot disappear? I don't have the software open at the moment to check this.
New ContributorHi,
thanks for the help.
yes, i agree regarding the possibly misleading documentation. (who is authorized to approve that?)
regarding the "Customize clocks for A and B ports",
yes it is impossible to generate byte_enable for the ports.
when selecting such clocking scheme i get the below error :
Error: stx10_fpga_dpmram512x128.ram_2port_0: In 'Clks/Rd, Byte En' tab, 'Emulate TDP dual clock mode' must be enabled if clocking method is 'Customize clocks for A and B ports' for Stratix 10 while using two read/write ports.
So I'm adding the TDP emulation check mark.
Then I select to have byte_enable (for port A for example)
And get the below error
Error: stx10_fpga_dpmram512x128.ram_2port_0: In 'Clks/Rd, Byte En' tab, 'Byte Enable Ports' are unavailable while using 'Emulate TDP dual clock mode' feature.
