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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Stratix 10 - 10G LL MAC Ignoring Set_False_Path commands in auto-generated SDC file

I used Quartus Pro 19.1 to generate a sample design using the 10G LL MAC for the Stratix 10. I slightly modified the sample design and integrated it into my larger design for the Stratix 10.

When I go to compile it I find that there many timing errors with the clock driving the 10G LL MAC. When I look at the Fitter warnings I see that it is ignoring all of the False Path settings from the low_latency_10G_ethernet.sdc. When I compiled the sample design I did not see these warnings.

Any clue what could be causing the Fitter to ignore the False Path settings? The SDC file uses wildcards to prevent any path changes from causing issues.

Here is a partial example of the warning.

Info (332104): Reading SDC File: '../altera_eth_10g_mac/alt_em10g32_191/synth/low_latency_10G_ethernet.sdc'
Warning (332174): Ignored filter at low_latency_10G_ethernet.sdc(249): *alt_em10g32_creg_top:creg_top_inst|alt_em10g32_creg_map:alt_em10g32_creg_map_inst|pri_macaddr_bit31to0[*] could not be matched with a register File: ../alt_em10g32_191/synth/low_latency_10G_ethernet.sdc Line: 249
Warning (332049): Ignored set_false_path at low_latency_10G_ethernet.sdc(249): Argument <from> is an empty collection File: ../alt_em10g32_191/synth/low_latency_10G_ethernet.sdc Line: 249
    Info (332050): set_false_path -from [get_registers {*alt_em10g32_creg_top:creg_top_inst|alt_em10g32_creg_map:alt_em10g32_creg_map_inst|pri_macaddr_bit31to0[*]}] -to [get_registers {*alt_em10g32_tx_top:tx_path.tx_top_inst|*}] File: ../alt_em10g32_191/synth/low_latency_10G_ethernet.sdc Line: 249
Warning (332049): Ignored set_false_path at low_latency_10G_ethernet.sdc(250): Argument <from> is an empty collection File: ../alt_em10g32_191/synth/low_latency_10G_ethernet.sdc Line: 250
    Info (332050): set_false_path -from [get_registers {*alt_em10g32_creg_top:creg_top_inst|alt_em10g32_creg_map:alt_em10g32_creg_map_inst|pri_macaddr_bit31to0[*]}] -to [get_registers {*alt_em10g32_rx_top:rx_path.rx_top_inst|*}] File: ../alt_em10g32_191/synth/low_latency_10G_ethernet.sdc Line: 250

10 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Can you provide the design for investigation? I think the problem is on the target of the get_registers command. What is the software version and edition?

    Thanks.

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      See the picture for the quartus version.

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi YY,

      I sent you the project via private message.

      Thanks.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I have filed a case to engineering team for investigation. I will provide an update once I received their reply.

    Thanks.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    The 10G BASE-R example design with VHDL language is generated and compiled with no SDC warning by using v19.1. You may refer to the working-fine design in the attachment. I found out the wrapper file of your attached design has been modified. Hence, the warning should be introduced by your modification.

    Thanks

    • DZuck1's avatar
      DZuck1
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago
      The sample you sent me is all in Verilog. It seems that when it is converted over to VHDL then it starts to have issues.
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I compared the design attached and the example design, I found out that the ignored constraints are due to the missing address decoder in the design attached. I tried to locate every missing registers specified in the ignored constraints in example design, these registers' input are from dut_inst|address_decoder_inst|mm_interconnect_0|mm_to_mac_0_avalon_universal_slave_0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|*, which is missing in the design attached (see attached set_false_path.txt).

    I checked with the team, the HDL file types option is supported for IP level and not for other files which is not .ip based. Customer can make modification on the wrapper file in any languages depends on their needs but there is only one type of HDL language for non-IP based file as this is just an example design.

    Thanks