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DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Stratix 10 - 10G LL MAC Ignoring Set_False_Path commands in auto-generated SDC file

I used Quartus Pro 19.1 to generate a sample design using the 10G LL MAC for the Stratix 10. I slightly modified the sample design and integrated it into my larger design for the Stratix 10. When I ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

The 10G BASE-R example design with VHDL language is generated and compiled with no SDC warning by using v19.1. You may refer to the working-fine design in the attachment. I found out the wrapper file of your attached design has been modified. Hence, the warning should be introduced by your modification.

Thanks

  • DZuck1's avatar
    DZuck1
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago
    The sample you sent me is all in Verilog. It seems that when it is converted over to VHDL then it starts to have issues.