State Machine to Drive DDR Controller works but does not.

Hi,

I am trying to read and write data to the SDRAM on the Altera DE2 board with Cyclone EP2C35F672C6 I checked the working of the DDR Controller using the example driver. I then replaced the example driver for the DDR Controller with my own State Machine.

To troubleshoot - I assigned SW[1] and SW[2] as user requesting read and write. The address is constant and so is the data. Cannot be any simpler, no! :(

I write data and then read again. The data I read back is different from what I have written. The problem is - I do not know if read is not working, or write is not, or perhaps both are not.

Apparently they both seem to work.

wdata_req goes high - and data seems to get written

rdata_valid goes high - and data seems to be read

But they don't match.

I am using the DE2 board, and I followed instructions in here to set it up:

http://www.altera.com/literature/an/an380.pdf

After setting it up, I got rid of the example driver file and put in my grand state machine that I wish would work.

I get errors for the ddr_a pins:

Info: Pin ddr_a[0] has GND driving its datain port

..

Info: Pin ddr_a[12] has GND driving its datain port

(Perhaps because of the fixed addresses?)

I am attaching my project (compute.v) is the top level file. It is messy and almost embarrassing to post.

--- State Machine Summary---

user_read_req = SW[1]

user_write_req = SW[2]

State 0:

If user_read_req goto State 1

If user_write_req goto State 4

for read:

State 1:

If local_ready goto State 2, user_read_req=0

Else user_read_req = 1, Stay in State 1

State 2

If rdata_valid goto State 3

Else stay in State 2

State 3

If rdata_valid stay in State 3 (keeps latching data to user_rdata)

Else goto state 7

for write:

State 4:If local_ready goto State 5

Else stay in State 4, user_write_req =1

State 5

If wdata_req goto State 6 (supply wdata and addr - always set) user_write_req=0

Else stay in State 5 (wait for wdata req)

State 6

If wdata req stay in State 6 (keep supplying wdata and addr)

Else goto State 7

resting state

State 8Stay here until read and write req are 0.

Then goto State 0.

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Somebody please help me figure this out. I am stuck on this since forever! What am I doing wrong :(