Altera_Forum
Honored Contributor
8 years agoSPI to Avalon MM Master IP
Hi
I am greatly confused by the SPI to Avalon MM Master IP core in Quartus Prime (16.0). After referring to the online documentation https://www.altera.com/documentation/sfo1400787952932.html#iga1401395000089 and https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf I only have more questions. It seems that the IP core uses encoding in the byte streams. Why is this done and is it possible to turn this off? It seems like an unnecessary step in data processing for the SPI master. Additionally, the read and write processes that illustrated look identical, I'm sure this can't be intentional. What is the "Command" byte sequence that is referred to in these images? I have so many questions! Can someone help me to understand this process better? Thanks in advance.