SPI Core

If you read the RXDATA register, that's the data that was received during the last completed transmission. Your code could do something like this:

1. Write command to TXDATA

2. Wait long enough for all bits to be clocked out (or use RX ready interrupt)

3. Read received data from RXDATA

4. Go to step 1

So the data read in step 3 is what was received during step 1 and there are no dummy transmissions required.

I've used a periodic timer interrupt to handle an ADC where the ISR is structured like this:

1. Read RXDATA

2. Write command to TXDATA

3. Return

The first time the ISR is called, RXDATA is meaningless. The second time it is called, RXDATA is the result of the command transmitted by the first call to the ISR, and so on.

The period of the timer interrupt just has to be long enough for the transmission to complete.

I hope this helps.

Thank you!

I figured that was pretty much what I needed to do. I started out using the Altera HAL drivers, but very quickly found a couple of issues:

1.. The HAL driver only supports 8 bit transfers as supplied - although adapting it for the 16 bit transfers I need was not difficult.

2.. It is not designed for simultaneous transfers - which is a very common requirement on SPI interfaces. Once I took the time to understand how the driver was working the solution was rather obvious!

Again, thank you.

John

Glad to hear you got it sorted out.

I've got a few different SPI peripherals in my current design and they all need handling in slightly different ways, none of which really fit with the HAL driver.

Cheers

I have the same problem. I want to read in an ADC (LTC2351-14). I modifiet the altera_spi_hal to my needs but i only see 8 clks when i look at the signale on a osci. I tried both, reading the reg directly and using the altera cmd.

here is the modified code:

# include "alt_types.h"# include "altera_spi_regs.h"# include "altera_spi.h"

int alt_avalon_command(alt_u32 base, alt_u32 slave,

alt_u32 write_length, const alt_u16 * write_data,

alt_u32 read_length, alt_u16 * read_data,

alt_u32 flags)

{

const alt_u16 * write_end = write_data + write_length;

alt_u16 * read_end = read_data + read_length;

alt_u32 write_zeros = read_length;

alt_u32 read_ignore = write_length;

alt_u32 status;

alt_32 credits = 1;

IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(base, 1 << slave);

if ((flags & ALT_AVALON_SPI_COMMAND_TOGGLE_SS_N) == 0) {

IOWR_ALTERA_AVALON_SPI_CONTROL(base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK);

}

IORD_ALTERA_AVALON_SPI_RXDATA(base);

for ( ; ; ){

do{

status = IORD_ALTERA_AVALON_SPI_STATUS(base);

}

while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0 || credits == 0) &&

(status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0);

if ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) != 0 && credits > 0){

credits--;

if (write_data < write_end)

IOWR_ALTERA_AVALON_SPI_TXDATA(base, *write_data++);

else if (write_zeros > 0)

{

write_zeros--;

IOWR_ALTERA_AVALON_SPI_TXDATA(base, 0);

}

else

credits = -1024;

};

if ((status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) != 0){

alt_u32 rxdata = IORD_ALTERA_AVALON_SPI_RXDATA(base);

if (read_ignore > 0)

read_ignore--;

else

*read_data++ = (alt_u16)rxdata;

credits++;

if (read_ignore == 0 && read_data == read_end)

break;

}

}

do{

status = IORD_ALTERA_AVALON_SPI_STATUS(base);

}

while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0);

if ((flags & ALT_AVALON_SPI_COMMAND_MERGE) == 0)

IOWR_ALTERA_AVALON_SPI_CONTROL(base, 0);

return read_length;

}