SPI Core

If you read the RXDATA register, that's the data that was received during the last completed transmission. Your code could do something like this:

1. Write command to TXDATA

2. Wait long enough for all bits to be clocked out (or use RX ready interrupt)

3. Read received data from RXDATA

4. Go to step 1

So the data read in step 3 is what was received during step 1 and there are no dummy transmissions required.

I've used a periodic timer interrupt to handle an ADC where the ISR is structured like this:

1. Read RXDATA

2. Write command to TXDATA

3. Return

The first time the ISR is called, RXDATA is meaningless. The second time it is called, RXDATA is the result of the command transmitted by the first call to the ISR, and so on.

The period of the timer interrupt just has to be long enough for the transmission to complete.

I hope this helps.