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hi,guys
I have some trouble when I used HDMI 2.0 IP CORE on my own Arroa 10 board.
Nvidia GTX1060 is used HDMI 2.0 test signal source, connect to FPGA serdes pin through my own connect board. I can see pll is locked, and GXB is ready, and HDMI core is locked, but the trouble is vid_lock is always low.And HDMI RX core have aux_data, audio_data output but have no vedio_data(vid_data,vid_de,vid_h,vid_v) output.
But when I loopback TX&&RX, RX CORE can output all vedio_data successful,which tx is sent color bar generated by myself using HDMI_TX IP CORE .
Any idea what this could be? Thanks for any help!
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Hey Tiber, have you managed to solve this? I am at the same situation.. Exactly as you described, PLL locked GXB locked, core locked and sees parallel data coming from GXB. But vid_lock is low and nothing comes out from the vid_ interface..
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