Some questions about SDRAM IP in Quartus 23.1std

Hi,

DE10-Standard comes with demonstration code, e.g. project DE10_Standard_DRAM_RTL_Test. I did two checks:

1. Compiled the project as is in Quartus 24.1 Std. Although upgrade of some 16.1 IP (FIFO, PLL) is suggested, it compiles without errors.

2. Performed Auto-Upgrade to 24.1 IP, no problems.

There are some warnings related to project .sdc resulting in unconstrained IO pathes, that should be handled, but the basic SDRAM code is working well. This is just expectable because SDRAM interface code uses other than DDR RAM no FPGA specific hardware resources and can be freely ported between FPGA series and Quartus versions.

Regards

Frank