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STATEABC's avatar
STATEABC
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9 months ago

Some questions about SDRAM IP in Quartus 23.1std

I want to use SDRAM Controller IP in Quartus 23.1std, but I found that Quartus 23.1std does not support this IP. I also did not find a similar or new version of SDRAM Controller in Intel FPGA Intell...
Memory
sstrell's avatar
sstrell
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9 months ago

Well you didn't mention that you were using a dev kit.

So it's a Cyclone V: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=2#contents

The SDRAM is DDR3 and accessed via the HPS only, so you could create a Platform Designer system from scratch or use an example design from Terasic's resource page that would include the DDR3 IP: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=4#contents

Edit: whoops you mean this board: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081&PartNo=2#contents

But again, you can get an example design from the Resources page in the "CD" download: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081&PartNo=4#contents

  • STATEABC's avatar
    STATEABC
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    9 months ago

    Thank you. The DE10-STANDARD has 64MB SDRAM on the FPGA side and 1GB DDR3 on the HPS side. Now I want to control the SDRAM on the FPGA side.
    In the example design, the SDRAM Controller IP is used in Quartus 16.1 to read and write access to the 64MB SDRAM on the FPGA side. However, this IP is no longer supported in Quartus 23.1. So I want to know if there are other IPs that can replace the SDRAM Controller IP?