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I could manage with physical addresses below 4G.
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Ok (your device driver on the host end would have to deal with it).
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But my attempts to configure the PCIe avalon MM master that way fail - unless I set the master interface to 64bit - and the dma controller doesn't want to generate 64 bit slave addresses.
I can't actually see how the dma controller can actually generate long TLP for reads at all.
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The Qsys PCIe core (which it sounded like you were talking about) does not have a DMA controller. If using the Qsys PCIe core, you would then use a regular Avalon-MM DMA controller on the Avalon bus, which would use 32-bit DMAs to the TXS port of the Qsys PCIe core.
This thread has links to documents and code on how that core can be configured:
http://www.alteraforum.com/forum/showthread.php?t=35678 Cheers,
Dave
Honored Contributor
