Simple ethernet communication and Avalon

Yes the TSE MAC can be used without SoPC builder. The Avalon ST and Avalon MM interfaces are simply bus protocols. Those buses are used within SoPC builder but they don't have to be. You can most certainly write your own logic to talk to the MAC.

The Avalon MM specification is basically just a typical processor bus (address, write, read, data, etc).

The Avalon ST specification is for streaming data and allows for packet control and backpressure.

Jake

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Yes the TSE MAC can be used without SoPC builder. The Avalon ST and Avalon MM interfaces are simply bus protocols. Those buses are used within SoPC builder but they don't have to be. You can most certainly write your own logic to talk to the MAC.

The Avalon MM specification is basically just a typical processor bus (address, write, read, data, etc).

The Avalon ST specification is for streaming data and allows for packet control and backpressure.

Jake

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Could you elaborate more on how to use the Avalon MM interface. I instantiated the TSE (no Qsys, no Nios) and I was trying to initialize the MAC by configuring the registers through verilog code, but I always read zeros from any field, even after writing one. I tried to configure the command_config register for example by using 8'h02 as address and read the TX_EN and RX_EN. I see that the address signal on the TSE interface is 8bits wide and I am not sure if I am doing the addressing properly. Also, when is data available after issuing a read command for example, in the same clock cycle or after one clock cycle? The waitrequest signal is high for three cycles and goes low for one cycle, and that repeats periodically for a continuous read operation at the same address being issued in each clock cycle, so I assume I get to actually read or write?... :(

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

The ug_ethernet isn't very elaborate on the details, but I think you can expect timing similar to Figure 3-3 in section 3.5.1 of the mnl_avalon_spec.pdf

a) hold 'read' and 'address' constant while 'waitrequest' is asserted.

b) when 'waitrequest' goes low, drive 'read' low.

c) on the next clock, 'readdata' should have valid contents.

The read transaction is being accepted by the TSE on the single cycle where read=1 and waitrequest=0, and then the contents are (probably?) output on the next clock.

As far as addressing goes, I believe you understand it correctly and simply need to supply the values from the 'Dword offset' column in Chapter 6 of ug_ethernet.pdf The value 0 should get you the 'rev' register, which is probably a good starting point.

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https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

The ug_ethernet isn't very elaborate on the details, but I think you can expect timing similar to Figure 3-3 in section 3.5.1 of the mnl_avalon_spec.pdf

a) hold 'read' and 'address' constant while 'waitrequest' is asserted.

b) when 'waitrequest' goes low, drive 'read' low.

c) on the next clock, 'readdata' should have valid contents.

The read transaction is being accepted by the TSE on the single cycle where read=1 and waitrequest=0, and then the contents are (probably?) output on the next clock.

As far as addressing goes, I believe you understand it correctly and simply need to supply the values from the 'Dword offset' column in Chapter 6 of ug_ethernet.pdf The value 0 should get you the 'rev' register, which is probably a good starting point.

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Thanks, that was really helpful. Finally managed to do it....:cool: