https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf
The ug_ethernet isn't very elaborate on the details, but I think you can expect timing similar to Figure 3-3 in section 3.5.1 of the mnl_avalon_spec.pdf
a) hold 'read' and 'address' constant while 'waitrequest' is asserted.
b) when 'waitrequest' goes low, drive 'read' low.
c) on the next clock, 'readdata' should have valid contents.
The read transaction is being accepted by the TSE on the single cycle where read=1 and waitrequest=0, and then the contents are (probably?) output on the next clock.
As far as addressing goes, I believe you understand it correctly and simply need to supply the values from the 'Dword offset' column in Chapter 6 of ug_ethernet.pdf The value 0 should get you the 'rev' register, which is probably a good starting point.
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