New Contributor
New ContributorHi Wincent,
According to this timing analyzer report, clocking signaltap with coreclkout will create clock transfers between test_out and signal tap nodes. The test_out is being clocked out by pld_clk. The problem is that signaltap complains that PLD_CLK is not running even after PCIe end point successful enumerates.
Do we need to write any value on test_in bus to make the pld_clk run? The stp file is called pcie_dbg.stp in the zip file that I attached early on in the post. Let me know if you have trouble accessing it.
Thank you.
Best regards,
Sanjay
Regular ContributorHi,
By right you should be able to use the coreclkout_hip as a signal tap sampling clock.
As a start, you can set the trigger on ltssm transition (this is done and confirm by you in previous command), by right you should able to see corresponding signals in the test_out bus.
I check with our internal team, timing violations with the test_out bus is ok, as this interface is purely debug interface.
The problem is that signaltap complains that PLD_CLK is not running even after PCIe end point successful enumerates.
>> If you need to remove timing errors, maybe you can try to synchronizing the deassertion of nPor to free running 1000Mhz clock to avoid plc_clk not running after pcie endpoint success enumerate
>> I dig deeper into the altpcie_a10_hip_pipen1b.v module and found that nPor is being used straight up as a reset on various registers in the pld_clk domain
>> my understanding that Npor resets the entire IP Core and transceiver.
>> Reset logic like PERSTn, nPor and/or local_rstn are written in Verilog at top level file.
Maybe you can try that and see if you are able to get it up.
Let me know if you still have any concern, Apology that I never try this till so deep, but I will try my best to assist you.
Regards,
Wincent_Intel
