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ALMSlinger's avatar
ALMSlinger
Icon for New Contributor rankNew Contributor
2 years ago

Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]

Hello, I am using pld_clk as signaltap clk to sample the test_out[319:0] signals of the pipe interface in Arria10GX HIP. But on the board the signaltap complains that pld_clk was not found. This h...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Kindly find the updated FTA for the PCIe debugging which is available in Intel Website .

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

>> click on Debug

  1. In the 4th tab of the spreadsheet, it says to use test_out to observe PCIe PIPE interface signals.
  2. you can refer to the 'Diagram' tab in the PCIe FTA excel sheet, which shows a screen shot of 'Expected behaviour for rxstatus, phystatus, txelecidle, txdetectrx' as an example.

For the test out signal, you can ignore it , for the test_in, you should focus on the PCIe IP top level signal, which is 32bit , you can refer to the user guide about it

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01145_avmm-1_0.pdf


Hope that able to help you to move forward.


Regards,

Wincent_Intel


  • ALMSlinger's avatar
    ALMSlinger
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thanks Wincent for digging this out. I had seen this before. Unfortunately, the spreadsheet doesn't say which clock to use to sample test_out. I don't undersand what you mean by ignoring the test_out signal. I want to see what is on the following signals.

    So I am asking again - what clock should I use in signaltap to sample these signals?

    rxvalid01test_out [86]test_out [246]
    rxblkst01test_out [85]test_out [245]
    rxsynchd02test_out [84:83]test_out [244:243]
    rxdataskip01test_out [82]test_out [242]
    rxdatak04test_out [81:78]test_out [241:238]
    rxdata032test_out [77:46]test_out [237:206]
    powerdown02test_out [45:44]test_out [205:204]
    rxpolarity01test_out [43]test_out [203]
    txcompl01test_out [42]test_out [202]
    txelecidle01test_out [41]test_out [201]
    txdetectrx01test_out [40]test_out [200]
    txblkst01test_out [39]test_out [199]
    txsynchd02test_out [38:37]test_out [198:197]
    txdataskip01test_out [36]test_out [196]
    txdatak04test_out [35:32]test_out [195:192]
    txdata032test_out [31:0]test_out [191:160]

    Thank you for the help.

    Best regards,

    Sanjay

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 years ago

      Hi,

      I am unable to trace the .stp file, can you please attach the .stp file separately here ?
      normally for pcie cases, we suggest to use either

      1. dut_coreclkout_hip_clk

      2. dut|dut|altpcie_a10_hip_pipen1b|coreclkout

      3. if not solved maybe you can try out using pld_clk

      Can you please try it and get back to me for your result ?

      Regards,

      Wincent_Intel