SGDMA - TSEMAC - SGDMA Loopback problem. TSEMAC internal loopback.

HI,

I am sorry I am not familiar with C-code, hence I won't be able to help you review your C-code design but I can try my best to provide TSE debug suggestion to you.

• Your TSE IP setting looks fine except do you use the "align packet to 32 bits boundary" setting ? Certain OS application may need this setting

In general, I would recommend you to check out Intel TSE user guide doc as usage and debug reference.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Let me summarize your problem statement to make sure I understand your issue correctly.

1. You found out some issue with TSE statistic counter

• I forgot to ask you are using which FPGA product and which Quartus version. Pls upgrade to latest Quartus version if possible to avoid old known issue as indicated in below KDB link
  • https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/kdb-filter.html?partialfields=type%3Ahow-to%2Ctype%3Aerrata%2Ctype%3Aanswers
  • Just go search "triple speed ethernet counter" in above KDB link to check out known issue list on TSE statistic counter and make sure your design is not impacted

1. Your TSE MAC loopback Avalon ST RX data is different from TX sent data

• My concern is maybe your Avalon ST TX data sent to TSE MAC is already corrupted hence the MAC loopback RX data is wrong as well
  • Or maybe TSE internal FIFO is already full but you still continue sent TX data causing packet drop situation
  • Or is there any potential Quartus design timing closure issue ? Have you verified in Quartus timequest ?
  • That's why I asked you to signal_tap both Avalon ST Tx data and Avalon ST Rx data traffic to compare result. Pls trigger on error signal (rx_err[5:0]) to check when failure happen and let me know which error type that it captured
  • If you found out something wrong with TX data transmission then you can back track to check out your TX_SGDMA IP

1. Sometime you observed aFrameCheckSequenceErrors (CRC error)

• My first question to you is how do you configure CRC insertion in TSE IP ? (command reg tx_cmd_stat[bit 17])
  • Do you let TSE IP compute the CRC or your software application needs to provide the correct CRC ?

1. TSE MAC loopback guideline

• You can find out more about loopback usage in chapter 4.1.9 MAC Local Loopback. It also suggest you to check for other statistic counter as well

1. Lastly, have you follow user guide doc chapter 5.3.1 guideline to initialize TSE IP correctly during power on ?

Thanks.

Regards,

dlim