Contributor
Super ContributorIn your equations, you're missing the clock skew, the difference between the clocks arriving at the FPGA and the downstream (output) device. So the equations should be (given that you know that downstream device's Tsu and Th):
output max = data trace (max) - clock skew (min) + Tsu
output min = data trace (min) - clock skew (max) - Th
It's OK if the min value is negative.
ContributorHi @sstrell
I only shown few constrains in my original message. I also constrained the following which was flagged as unconstrained.
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -setup -rise_from clk -rise_to clk 0.2
set_clock_uncertainty -hold -rise_from clk -rise_to clk 0.2
set_clock_uncertainty -setup -rise_from clk_virt -rise_to clk 0.2
set_clock_uncertainty -hold -rise_from clk_virt -rise_to clk 0.2
set_clock_uncertainty -setup -rise_from clk -fall_to clk 0.2
set_clock_uncertainty -hold -rise_from clk -fall_to clk 0.2
set_clock_uncertainty -setup -rise_from clk -rise_to clk_virt 0.2
set_clock_uncertainty -hold -rise_from clk -rise_to clk_virt 0.2
#Determine internal clock uncertainties
derive_clock_uncertainty
