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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Serial Lite III "start_of_burst" and "end_of_burst"

I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Thanks for trying to help - but you're incorrect.

In my use case - I'm de-asserting valid so by definition I'm using BURST MODE - and NOT continuous mode.

The data I'm sending is NOT "packet oriented" - so although valid isn't continuous my data stream can be treated as a SINGLE INFINITE PACKET.

So in my use case:
1. I have to assert "start_of_burst" (on the first valid).

2. I don't have to assert "end_of_burst" - because my packet NEVER ENDS.

I simulated the design with discontinuous valid and "end_of_burst" tied to GND - and it works fine.