SERDES IP core for LVDS interfacing

Hello everyone,

I need to do some video bypassing project on Cyclone V FPGA, which receives video from 28bits DVI and serialize them to 4bits LVDS interface, in order to display the video on LCD screen. For that I need to implement an SER IP to perform DVI to 4bits LVDS conversion. I found some documents provided by Altera in 2007 about SERDES megafunction IP core. Howeve I can't find anything similar in my Quartus14.0 IP Catalog, It turns out that this IP core is not free anymore, instead, the IP core is called Video LVDS SERDES Transmitter/Receiver and is sold by Microtronix(https://www.altera.com/products/intellectual-property/all-ip/dsp/additional-functions/m-mtx-lvds-serdes.html). Does anyone know how to implement a Serialization transmitter that make 7:1 Serialization from scratch? Thanks a lot.