SDRAM Controller - Problems with reading

First off, I'd stick a scope on the signals to the SDRAM, and check they are doing something sane.

You should be able to see the clk running, and the various control signals moving around.

The DQ signals should be moving too. On DDR memory at least you can see which end is driving them because the FPGA tends to have a stronger drive strength than the memory. That will tell you if the read commands are getting to the memory.

Hi Cajun,

I am already watching several of my own signals and the wait_request coming from the SDRAM Controller.

I think it's a good idea to watch the SDRAM Controller signals too.

Let me try it.

Kind regards,

Ahmet

Hi @ All,

now it looks as if I can read from the SDRAM. But the read_data is always the same as the write_data. => I think it still doesn't read the SDRAM.

The DQ signals are changing.

PS: I had to use the evaluation board to get read_data, as our board also doesn't work. :-(

After removing the SDRAM component from the board I discovered that I get the same results from the board, even if the SDRAM is missing.

Does anybody know how I can solve the problems reading the SDRAM?

Thanks a lot!

Ahmet

Ahmet, I would first write data and then try to read back from the same location.

Are you using Altera's DDR Megafunction? If you are -- they include an example driver with it. I would try to see if that works before anything else.

I still recommend sticking a scope on all the pins of the SDRAM and checking them against what you are seeing in simulation.

If you don't have access to a quick enough scope, one solution is to start with a working design (easy in the case of the Altera dev. boards) and slowly morph it into your design.

@ Kitty: It's not a DDRx SDRAM Controller that I used. It's just the SDRAM Controller from SOPC (lowest in list).

I also think it is a good idea to get a working example. Anybody knows where to find some?

There are no suitable reference designs for SDRAM Controllers. They are either in Verilog (I need VHDL), or I can't see any codes and it does not compile.

When I just write a single address and read it out, it looks good. But when I write about 12 addresses and try reading out, I just get FFF.. instead of the data.

My code is attached, in case you want to have a look at it (for several read/write cycles).

Next think I want to try is checking the timing, try only 12.5MHz clock and reading the SDRAM Controller Documentation.

What else can I do? Where can I find a working design with an SOPC SDRAM Controller in VHDL?

Thanks in advance!

Hey,

it worked with half the clock frequency (=> 12.5 MHz). :D

Actually I need 50 MHz, but that's another thing.

Yippiii!