SDRAM Controller - Problems with reading

There are no suitable reference designs for SDRAM Controllers. They are either in Verilog (I need VHDL), or I can't see any codes and it does not compile.

When I just write a single address and read it out, it looks good. But when I write about 12 addresses and try reading out, I just get FFF.. instead of the data.

My code is attached, in case you want to have a look at it (for several read/write cycles).

Next think I want to try is checking the timing, try only 12.5MHz clock and reading the SDRAM Controller Documentation.

What else can I do? Where can I find a working design with an SOPC SDRAM Controller in VHDL?

Thanks in advance!