SDI Transmit Triple Rate on Cyclone V

Hello all, I'm having issues trying to get a triple rate SDI transmit only module up and running on a Cyclone V dev kit. I can get 1080P60 out working fine using a pattern gen as an input to the CVO block and then out through the SDI transceiver block.

However when I write to the pattern generator to change to 720p for example then no signal is detected on the SDi test kit.

Altera's examples all seem to revolve around loopback and RX examples and so nothing is easily seen to port over to my design.

Some assumptions I have made include the fact that I believe the TX transceiver does not require reconfiguration. Is this the case, it's not 100% clear from the Alter docs but I believe TX reconfig is only required when switching from PAL to NTSC ie switching between 148.5 and 148.35 MHz clock references. To that end I have left the reconfig to and from xcvr ports unconnected.

I was expecting the tx_std signals from the CVO block to let the SDI block know what's coming and structure its behaviour accordingly.

Be grateful if any of you out there have any hints if you've done this before as time is of the essence. (Funnily enough I managed to get triple rate RX working fine from an example design, just tx I'm having and issue with) .

Below is my instantiation of the SDI block if it give you any info.

SDI2_TR_TXONLYInst : SDI2_TR_TXONLY

port map (

tx_rst => sResetSdi,--: in std_logic

tx_enable_crc => '0',--: in std_logic

tx_enable_ln => '1',--: in std_logic

tx_ln => ssdi_cvo_vid_ln,--: in std_logic_vector(10 downto 0)

tx_std => ssdi_cvo_vid_std,--: in std_logic_vector(2 downto 0)

tx_datain => ssdi_cvo_vid_data,--: in std_logic_vector(19 downto 0)

--tx_datain_valid => '1',--: in std_logic

tx_datain_valid => sdata_valid,--: in std_logic

tx_trs => ssdi_cvo_vid_trs,--: in std_logic

tx_ln_b => (others => '0'),--: in std_logic_vector(10 downto 0)

tx_dataout_valid => sdata_valid,--: out std_logic;

tx_pclk => ssdi_cvo_vid_clk,--: in std_logic

tx_coreclk => clk_148_p,--: in std_logic

xcvr_refclk => clk_148_p,--: in std_logic

sdi_tx => sdi_tx_p,--: out std_logic;

tx_pll_locked => open,--: out std_logic;

tx_clkout => ssdi_cvo_vid_clk,--: out std_logic;

reconfig_to_xcvr => (others => '0'),--: in std_logic_vector(139 downto 0)

reconfig_from_xcvr => open, --: out std_logic_vector(91 downto 0);

pll_powerdown_in => spll_powerdown,--: in std_logic_vector(0 downto 0)

pll_powerdown_out => spll_powerdown--: out std_logic_vector(0 downto 0)

);

Thanks for any help.