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PVanL's avatar
PVanL
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Scripts from Quartus in Modelsim not using the latest files when compiling

I am using quit a while Modelsim (DE-64 2020.3), in which i change and add files to the examples generated by Quartus 20.2. So far successfully, in the sense, that Modelsim behaves as expected. In this particular case: PCIe example with ST Avalon.

For a few days however, Modelsim seems does no longer to recognize changes to files, and somehow keeps on using libraries of earlier compiles. The scrips as generated by Quartus are unchanged, in fact it seems, but not consequently, that the scripts are not well read. For instance, a script like in modelsim_files.tcl like:

lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS {+incdir+[normalize_path "$QSYS_SIMDIR/../altera_pcie_a10_tbed_191/sim/"]} \"[normalize_path "$QSYS_SIMDIR/../altera_pcie_a10_tbed_191/sim/altpcietb_bfm_rp_gen2_x8.v"]\" -work altera_pcie_a10_tbed_191"  lappend design_files "vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS {+incdir+[normalize_path "$QSYS_SIMDIR/../altera_pcie_a10_tbed_191/sim/"]} \"[normalize_path "$QSYS_SIMDIR/../altera_pcie_a10_tbed_191/sim/altpcietb_bfm_rp_gen2_x8_01.v"]\" -work altera_pcie_a10_tbed_191"

may still rever to a previous version altpcietb_bfm_rp_gen2_x8.v or an earlier version of altpcietb_bfm_rp_gen2_x8_01.v. However, if i insert a syntax error, it does see the syntax error and generates an error. If the modified code is syntaxtly correct, it does not see the new version, and reuses an earlier version of the library.

Any idea what is happening here?

regards,
Pieter

4 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Could you try to clean and rebuild the project? See if it helps.

    Try to install the latest Quartus 20.3 and see if the problem persists.

    • Chris2000's avatar
      Chris2000
      Icon for New Contributor rankNew Contributor
      5 years ago

      I'm having the same problem with 20.3.

      Project -> Clean Project did not help.

      \sim\mentor\common\modelsim_files.tcl does not get updated when I generate HDL or TB in Platform designer or compile the FPGA or Generate Testbench system.

      What action causes this file to be created/updated?

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Sorry for idling for sometime. Do you able to solve the issue?

        Have you try go to Tools > Generate Simulator Setup Script for IP in the Quartus Pro? It should generate the modelsim _files.tcl for the IPs used.