Forum Discussion
Could you try to clean and rebuild the project? See if it helps.
Try to install the latest Quartus 20.3 and see if the problem persists.
I'm having the same problem with 20.3.
Project -> Clean Project did not help.
\sim\mentor\common\modelsim_files.tcl does not get updated when I generate HDL or TB in Platform designer or compile the FPGA or Generate Testbench system.
What action causes this file to be created/updated?
- RichardT_altera5 years ago
Super Contributor
Sorry for idling for sometime. Do you able to solve the issue?
Have you try go to Tools > Generate Simulator Setup Script for IP in the Quartus Pro? It should generate the modelsim _files.tcl for the IPs used.
- RichardT_altera5 years ago
Super Contributor
Customer able to solve the problem and the problem is for some reason system created a library 'work' where the newly compiled version of altpcietb_bfm_rp_gen2_x8.v was, but in executing, it used /libraries/work, where a previous compiled version was.