SATA host IP for cyclone IV GX ?

Hi Ironmoose,

I am attempting to implement SATA in a Arria II GX. Can you recommend a SATA analyzer to make the task easier?

Thanks.

Thanks Ironmoose.

Do you remember how much it cost?

Thanks.

Ironmoose,

I know you said that you could not share the source code for your project. But, would it be possible to share the settings for the transceivers? I assume you used altgx blocks. I am about to go through the process of trying to figure out all the setting far the altgx mega-wizard.

Thanks.

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Here you go. You will have to monkey around with the settings to turn the correct options on. Some options depend on settings on the following pages to be enabled.

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Thanks. This will be very helpful. I appreciate it.

Ironmoose,

I’m trying to implement the SATA protocol using the Stratix 4 ALTGX transceiver.

We have our own SATA controller.

We are doing the 8b/10b encoding in the link layer as the

SATA standards specifies.

However in the “Transceiver Architecture in Stratix IV Devices” document it says:

In Basic functional mode, you can enable the optional rx_signaldetect signal (used

for protocols such as SATA and SAS) only if you select the 8B/10B block.

This will not work for us. We need the rx_signaldetect signal, but we can’t do

the 8b/10b in the PHY layer since we are already doing it in the link layer.

how did you get around this problem.

I did noticed that is easy to trick MW into providing the rx_signaldetect output without having to select 8b10b encoding, and it does seem to work in simulation, but will it

work in real hardware?

skg

Yes, I noticed that you cannot have one without the other. We used the 8B/10B block provided by the mega wizard and that worked fine. The ALTGX will give you the PHY layer and the 8B/10B. You will then need to add the scrambler and the rest on top of that to complete the link layer.

Is there a reason you are not using the 8B/10B provided by the ALTGX config?

thanks ironmoose for your reply;

The reason we cannot do 8b/10b in the PHY is because our SATA controller already does it in the link layer. we would have to bypass the 8b/10b in the link layer in order to use the one in the ALTGX. I am using the FPGA to emulate an ASIC and the PHY in the ASIC does not have

8b/10b encoding.

An Altere FAE told me that another customer had tricked the MW to provide the rx_signaldetect without selecting 8b/10b and it worked for them. So, I am thinking of trying that myself.

The way to trick MW is to select 8b/10b and then select the rx_signaldetect port and then

unselect the 8b/10b and the rx_signaldetect port remains there. I tried it in simulation and it

does do the right thing. I was able to do the COMRESET/COMINIT sequence.

Another question I have is how did you do change the speed of the ALTGX? The appnote recommends two methods. 1) have 3 mif files one for gen1, gen2, gen3 and then use the altgx_reconfig block to change the config of the altgx. 2) use the rate_switch_cntrl to change the clock divider to 1, 2, or 4 to change the tx clock.

I tried method 2 which is easier to implement and it worked in simulation.

skg