SATA host IP for cyclone IV GX ?

thanks ironmoose for your reply;

The reason we cannot do 8b/10b in the PHY is because our SATA controller already does it in the link layer. we would have to bypass the 8b/10b in the link layer in order to use the one in the ALTGX. I am using the FPGA to emulate an ASIC and the PHY in the ASIC does not have

8b/10b encoding.

An Altere FAE told me that another customer had tricked the MW to provide the rx_signaldetect without selecting 8b/10b and it worked for them. So, I am thinking of trying that myself.

The way to trick MW is to select 8b/10b and then select the rx_signaldetect port and then

unselect the 8b/10b and the rx_signaldetect port remains there. I tried it in simulation and it

does do the right thing. I was able to do the COMRESET/COMINIT sequence.

Another question I have is how did you do change the speed of the ALTGX? The appnote recommends two methods. 1) have 3 mif files one for gen1, gen2, gen3 and then use the altgx_reconfig block to change the config of the altgx. 2) use the rate_switch_cntrl to change the clock divider to 1, 2, or 4 to change the tx clock.

I tried method 2 which is easier to implement and it worked in simulation.

skg