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Sai2403's avatar
Sai2403
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7 months ago

Regarding MIPI CSI 2 TX

Hi, In my Project, I have to generate test pattern data and send it to MIPI CSI 2 via AXI stream, and MIPI CSI 2 will send the pixel data to link_0 of MIPI DPHY IP , but when i try to simulate the de...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
5 months ago

Hi Sai,

Sorry, I missout your reply in a month ago.
Please @ me so that I get the notification from any of your future reply.
For the HW MIPI TX design, our team is currently working to provide it. 

hi wincent, FYR attached the snap shots.we set VCO freq to 600MHZ.
>> Sorry, I am little bit confuse with the waveform provided by you. Can you please clarified from where you see the things get wrong ?
>> So that I am looking apple to apple for your issue.

Regards,
Wincent

Sai2403's avatar
Sai2403
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5 months ago

Hi Wincent_Altera​ ,

Please refer the below attached snaps, these are the latest observations found on hardware.

if we observe clock images, dphy_clk is not continous , whereas dphy_data is contionous without any interruption. We are trying to get the clock.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    5 months ago

    Hi Sai2403​ ,

    Can you please show me your expected waveform (Simulation) as well ?

    Regards,
    Wincent_Altera

    • Sai2403's avatar
      Sai2403
      Icon for New Contributor rankNew Contributor
      5 months ago

      Hi Wincent_Altera​ , Please check this one. this is behavior of dphy data and clock lanes expected behavior onhardware

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        5 months ago

        Hi Sai2403​ ,

        From the simulation, I observed few things.

        • Signals with value 1'hx or 32'hxxxxxxxx:
          Several signals, including LINK0_CK_Enable, LINK0_CK_AplMode, LINK0_CK_TxHSIdleClkHS, reg_be_o, and reg_din_o are showing unknown (x) values.
        • Data Path Signals:
          Your LINK0_dphy_link_dp, LINK0_dphy_link_dn, LINK0_dphy_link_cp, and LINK0_dphy_link_cn show valid values at times, but there are also periods with x values.
        • Write/Read Enable:
          reg_wr_en_o and reg_rd_en_o are toggling, but when reg_be_o or reg_din_o are x, it means the bus is not being properly driven.


        I would suggest to check back your signal that showing x , Ensure all registers and outputs are initialized to known values when reset is asserted. 

        For your issue dphy_clk is not continous , whereas dphy_data is contionous without any interruption.
        >> It sound very unusual to me. If data is being sent while the clock is not running, the receiver cannot sample the data correctly. This indicates a protocol or state machine issue.
        >> Can you please try to synchronize your clock and data lane state machines
        >> Only allow data transmission when the clock lane is active and continuous.

        Regards,
        Wincent_Altera