Regarding MIPI CSI 2 TX

Hi Sai,

May I know which design that you are using ? 
is it custom design or the design generated from the design example ?

From your description, I understand that
mipi_dphy_0/LINK0_CK_Stopstate stays high throughout simulation.

• AXI-Stream ready goes high briefly (three cycles) then deasserts and stays low.
• You’re sending test pattern data over AXI-Stream to MIPI CSI-2, which then connects to MIPI D-PHY (link_0).

These symptoms typically indicate that the D-PHY high-speed (HS) clock lane never leaves Stop State, 
so the D-PHY never transitions to HS transmission, and upstream flow-control (through CSI-2 and AXI-Stream) stalls. 
AXI tready deasserting after a few cycles is consistent with small internal FIFOs filling while the downstream interface (D-PHY) is not transmitting.

Based on the description - please check on proper resets, clocking, enabling continuous HS clock, and performing the required configuration writes in your simulation testbench. 
Once the D-PHY clock lane begins toggling HS, LINK0_CK_Stopstate should go low, and tready should remain asserted under normal flow.
That could be a good start to check with. BUT that will be take time as it might be hard to narrow down the problem

Quick way that I would recommended will be to compare your design with the our design example 
https://github.com/altera-fpga/agilex-ed-camera-ai
That could help you to narrow down the problem faster if checking those parameter/ setting/

Regards,

Wincent_Altera