Reed Solomon IP Core

Hello Avatar,

I did file an SR. They told me that there were some issues with V4.1.0 (the one that I was trying to use) and asked me upgrade it V7.2. Hopefully this comes with some documentation or examples. Will post an update sometime early next week after I try with the updated version.

Regards,

Rohith

Hi Rohith,

While it is true that you should update to the newest version (two reasons: (1) 4.1.0 might have some bugs and (2) some improvements might have been made to the core since then), it will not solve your problem. Instead, I believe you are having problem understanding the lack of the clock port in your DSP Builder design. (Feel free to correct me if I am wrong).

Essentially there is probably nothing wrong with your DSP Builder design and the user guide. By default, you will not see the clock signal in DSP Builder design. The clock port is automatically hidden from the end user. However, it will be generated when the HDL is created. (If you want, you can find multiple DSP Builder design examples that I have posted on the forum-- simply do a search for my name).

With that being said, the timing diagrams were created to target HDL simulations. The good news is that, minus the clock signal, the control signals should still be useful for you when you are implementing your design in DSP Builder.

Hope this helps.

Hello WrongHorizon,

Thank you for explaining the absence of the clock signal. I am still confused though, because, if I do not know what the clock frequency is (or cannot set it), how do I set the rest of the control signals (sink_eop, sink_sop etc) to align with the rising edge of the clock .

As far as the design goes, my outputs do not make any sense, in fact I think it is just garbage (see attachment). I read through the documentation to build the control signals (although these are perfect square waves without any rise/fall times).

It is possible that this set up is completely wrong. Can you please point me to some simple examples involving the RS Encoder?

Thank you,

Rohith

Hi Rohith,

If no clock is specified, a default clock (corresponds to a real world clock w/20ns period and it corresponds to sample time of 1 in Simulink -- i.e. each sample time in Simulink corresponds to 1 cycle of clock) is used with DSP Builder design. If you want, you can always drag a clock block into your design (should be one of the blocks under altlib). Once you have that block in your design, double click on that and that's where you can enter two info (1) the real world period and (2) what the sample time is in Simulink (how many samples in Simulink should correspond to a cycle of the clock).

Looking at your simulation, it seems like you should change several settings. Make sure to configure your simulation to run as fixed-step and discrete simulation. (I believe this is what Altera recommends). Also make sure you don't interpolate data as well. That way you get something that resembles results obtained in hardware.

Also I believe the RS core uses the Avalon Streaming interface. Basically, you should pay close attention to the sink_ena output. When it is low, the RS core is not ready to take on more data. Therefore, you should not input any VALID data into the core during that time (i.e. sink_valid should be low and also make sure to hold your other outputs constant). Other than that, sink_sop should be asserted at start of codeword and sink_eop should be asserted at the end of the codeword.

Anyhow I created a quick-and-dirty example to show you what I was talking about.

To run it, simply regenerate the core and it should be ready to go. The example contains a simple (6,2) RS encoder - pretty much just default setting.

In this example, each sample in Simulink indicates one clock cycle. The real world clock has period of 20ns. DSP Builder will automatically add in the clock singal for you when you generate the HDL (via Signal Compiler).

Hope this helps.

Hello WrongHorizon,

Thank you so much for your inputs and the model. I really appreciate it. Since I haven't upgraded to 7.2, I wasn't able to open all the pieces. The DSP Builder blocks show up as "Bad Links". But with the explanation you provided on control signals, I'll rebuild it.

You were right with the Simulink Configuration Parameters. It should be fixed step, discrete and it might help to make it Single Tasking. I usually set these and then start working, but wanted to get some basic things going, so I missed it. Thanks for pointing it out.

The documentation with V4.1.0 mentioned that the encoder/decoder follows the Atlantic Interface. I am not sure if this is the same as The Avalon Interface (have attached the documentation I have). However, what you wrote makes more sense.

This is my first exposure to DSP Builder and Megacore functions, hence the mistakes, confusion and questions.

Thank you again, for the replies. Will keep this post updated with the results.

Regards,

Rohith

Hello WrongHorizon,

I am the in the process of upgrading to 7.2. Since I am working on another project, I probably won't get to try this out until next week.

Regards,

Rohith