Reed Solomon IP Core

Hi Rohith,

While it is true that you should update to the newest version (two reasons: (1) 4.1.0 might have some bugs and (2) some improvements might have been made to the core since then), it will not solve your problem. Instead, I believe you are having problem understanding the lack of the clock port in your DSP Builder design. (Feel free to correct me if I am wrong).

Essentially there is probably nothing wrong with your DSP Builder design and the user guide. By default, you will not see the clock signal in DSP Builder design. The clock port is automatically hidden from the end user. However, it will be generated when the HDL is created. (If you want, you can find multiple DSP Builder design examples that I have posted on the forum-- simply do a search for my name).

With that being said, the timing diagrams were created to target HDL simulations. The good news is that, minus the clock signal, the control signals should still be useful for you when you are implementing your design in DSP Builder.

Hope this helps.