Forum Discussion
MinzhiWang
Occasional Contributor
Occasional ContributorTranceiver Enhanced PCS Basic mode questions
Hello Guys, We used Arria GX and Straitx IV GX devices before, now we switch to use Cyclone 10 GX FPGA. I have several simple questions about XCVR's control port/signal. Why I can't see rx_control...
MinzhiWangOccasional Contributor
Occasional ContributorHello Ash,
Now we received our new hardware with 10cgx105f780e6s device. You said rx_enh_blk_lock will indicate word alignment achieving. But it only exists on receiver side. How TX knows XCVR link is ok or not?
Regards
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
In the Cyclone 10 GX Enhanced PCS, the TX side has no built-in lock indicator because the transmitter does not perform word alignment. TX link health is confirmed by the far-end receiver: the remote device's rx_enh_blk_lock (or its equivalent) signals that your TX data stream has been correctly aligned at the other end.
To surface this status locally, implement a feedback path in your FPGA logic that brings the remote RX lock signal back to your local TX domain.
Regards
- MinzhiWang
Hi Ash,
Two questions:
- Transimitter can send enough continous BC to ensure tranceiver link properly. During normal operation, for example, 60% time sending user data and the rest time have to send BC. How receiver can know which word is user data or BC (K chractors)?
- Now, we applied one simple test. Transmitter sends constant 32-bit data(h'0008feff), however, receiver receives correct data with MSB-16bit and LSB-16bit reversing, as the following image indication. How to deal with this issue?
Regrad
