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SharmaUmesh278's avatar
SharmaUmesh278
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1 month ago

MT25QL128 Not Available in ALTASMI_PARALLEL Configuration Device List

Hi everyone, I'm working on a design with Cyclone FPGA(s) in a master/slave (active/passive) configuration, using a Micron MT25QL128 flash device for FPGA configuration storage. While trying to ins...
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SharmaUmesh278's avatar
SharmaUmesh278
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14 days ago

Hi umut_arrow​ , FakhrulA_altera​ ,

Sorry for the late reply.

I have now verified that the MT25QL128 works with the EPCQ128/EPCQ128A setting in the ALTASMI_PARALLEL IP, and I am able to read the configuration data successfully.

At the moment, I am still validating the complete configuration sequence in my Cyclone IV  master and 10 LP slave (active/passive) FPGA setup. I have observed that the nSTATUS signal behaves as expected, but I am still investigating some aspects of the passive-device configuration flow. In particular, I am not yet seeing the expected behavior on signals such as nCONFIG, CONF_DONE, and the related configuration handshaking signals from the slave FPGA.

Based on the Active Serial configuration waveform and the configuration chapter for Active/Passive Cyclone FPGA configuration  ( 13. Configuring Cyclone FPGAs)  , I am checking whether the observed behavior is expected or whether there are additional timing or sequencing requirements that need to be considered.

Overall, the MT25QL128 appears to be compatible with the EPCQ128/EPCQ128A setting. However, I would appreciate any guidance regarding Passive Serial (PS) configuration of the slave device. Is there any reference VHDL code, example design, or Intel/Altera IP available for implementing the Passive Serial configuration sequence between the master and slave FPGAs?

Thanks and regards,

Umesh

FakhrulA_altera's avatar
FakhrulA_altera
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9 days ago

Hi Umesh,
 

Thank you for confirming that MT25QL128 works with the EPCQ128/EPCQ128A setting.

For AS multi-device configuration, no separate VHDL or IP is normally required. Set the master to AS mode and the slave to PS mode, with nCONFIG, nSTATUS, and CONF_DONE shared, and route DATA[0] and DCLK to the slave as described in the Cyclone 10 LP handbook. Please note that nCONFIG is an input, not a handshake output from the slave.


Please also verify the DCLK timing: start DCLK only after nSTATUS is high, and provide at least two additional falling DCLK edges after CONF_DONE rises. If necessary, enable a post-chain bitstream padding byte.

If the issue remains, please share one waveform showing nCONFIG, nSTATUS, CONF_DONE, DCLK, and DATA[0], together with the exact FPGA part numbers and Quartus version.


Best regards,
Fakhrul