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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

Arria10 no "EMIF_USR_CLK" out( DDR4), thus "EMIFDebug KIT" says “Could not accurately determin conne

hi all, we made a customer Arria10 SX Board, with total 4GB DDR4 on PL side ( using MT40A512M16LY-062E ). THE ddr4ref clock is "133.333MHz", we followed "ug-20115 EMIf Arria10 IP User Guide " t...
Rashmi1's avatar
Rashmi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hello,


I recommend that you check the following points :-

The DDR IP pll ref clock and the memory output clock to the DDR devices are both running and at the correct frequencies.

The DDR IP global_reset_n signal is high


Try reducing the frequency of the JTAG clock signal and see if this helps. See KDB :

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06242013_922.html


If these points don't help, can you confirm if your project is just the auto-generated example design project generated from the DDR IP or does it contain additional logic from your design ?


Thanks,

Intel Forum Support


  • JET60200's avatar
    JET60200
    Icon for Contributor rankContributor
    5 years ago

    Thanks @Rashmi1 for suggestion,

    we rollback to use Quartus Standard 18.1 to generate an EMIF Example Design, and it succeed to run on our A10SOC board. You can close this ticket. Thanks for help ~

    • APPU_appu's avatar
      APPU_appu
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      @Rashmi1 @JET60200

      Hi Rashmi /JET60200

      while debugging the DDR IP, i am getting the error like "Could not accurately determine connection type for connection PCIe_SUB_SYATEM|ddr4|emif_0|col_if|colmaster as the clock of the connection is inactive "

      can u please let me know how to debug this issue above one i tried but it is not working