Rashmi1
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Re: FPGA DDR4 Eye Mask
Hello, Please refer to the A10 EMIF datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf The information on eye diagram has been explained in section 11.4.2.2. Understanding Channel Signal Integrity Measurement of the above datasheet. Thanks.918Views0likes0CommentsRe: About FPGA: Does Cyclone V (5CEA7 F896) support DDR3
Cyclone V device overview document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf Cyclone V Device handbook , chapter 6 explains guidelines of using DQ/DQS pins : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf1.1KViews1like0CommentsRe: Intel Agilex DDR SI simulation kit
Hello, We do not have a SI simulation kit for SODIMM. We are not limited to any specific software to use. Customers can use any software to do their SI simulation. The SI simulation guideline has been explained well in EMIF user guide. Thanks, Intel Forum Support1.2KViews0likes0CommentsRe: Resource utilization of a 32-bit DDR3 controller in Cyclone 10 GX
Hi Paul, Please refer to EMIF C10 GX FPGA IP User guide. Link for the document: https://www.intel.com/content/www/us/en/programmable/documentation/mls1506089797502.html Refer to section 3: Intel Cyclone 10 GX EMIF IP Product Architecture , it goes over resource sharing . Section : 3.1.4.2 goes over implementing a X72 interface for example. We do not have anything to explain X32 i our documentation. Thanks, Intel Forum Support709Views0likes0CommentsRe: Arria10 no "EMIF_USR_CLK" out( DDR4), thus "EMIFDebug KIT" says “Could not accurately determin conne
Hello, I recommend that you check the following points :- The DDR IP pll ref clock and the memory output clock to the DDR devices are both running and at the correct frequencies. The DDR IP global_reset_n signal is high Try reducing the frequency of the JTAG clock signal and see if this helps. See KDB : https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06242013_922.html If these points don't help, can you confirm if your project is just the auto-generated example design project generated from the DDR IP or does it contain additional logic from your design ? Thanks, Intel Forum Support1.6KViews0likes2CommentsRe: Arria10 DDR4
HI Vivek, Please refer to EMIF sec estimator: https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html Plug in Device family, Speed grade, interface type, memory standard, clock rate etc or the available data you have and submit. Spec estimator will be able to provide you the information you are seeking. Thanks, Intel Forum Support998Views0likes1CommentRe: ARRIA 10 with DDR4
HI Lior, Sorry for not getting your question right in the first place. Yes, You can select 2666MT/S speed bin , but enter the timing values associated with 3200 MT/S referring to memory datasheet. Please enter Parameters dependent on speed bin, operation frequency and page size associate with 800 MHZ values. Hope this helps.1.1KViews0likes0Comments