Forum Discussion
Fresh_Leon
New Contributor
5 years agoFPGA DDR4 Eye Mask
Dear,
We are in FPGA (Arria 10) board design progress, our SI engineer are studying on DDR4 simulation.
Where could we find FPGA (Arria 10) DDR4 Eye Mask data (both write and read operation) ?
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Rashmi1
Occasional Contributor
5 years agoHello,
Please refer to the A10 EMIF datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf
The information on eye diagram has been explained in section 11.4.2.2. Understanding Channel Signal Integrity Measurement of the above datasheet.
Thanks.