JET60200
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Re: 仿真O-RAN Intel FPGA IP Example
Hi @Kshitij_Intel , Would you please help to check this thread that is related to ORAN IP Simulation? After We generate "ORAN + eCPRI IP" simulation project using Quartus Pro 21.3 , we saw ORAN C-Plane packets is generated normally, unfortunately there's no U-Plane DATA packet generated out ? Could you help this , ThanksRe: 仿真O-RAN Intel FPGA IP Example问题
Hi @yufuliang , thanks for update your result 冒犯打搅一下: 我们也在尝试英特尔 "eCPRI + ORAN IP" 来验证 ORAN 7-2 的方案，但遇到了跟你一样问题 (仿真工程中 C Plane 有数据，但 U Plane 一直没有数据出来~)。 是否是 Intel ORAN User Guide 文档有啥参数遗漏了， 您能讲下这个问题是具体怎么解决的吗 ？ ( 另外. 如果您能分享下最终正常仿真的 oran simulation 工程，那就太好了 ( 1684392931@qq.com )。 非常感谢 ~ Thanks & Best RegardsHow is A10 MSGDMA prefetch enabled core to transfer 128 descptors data from FPGA to CPU?
hello , We use Arria10 on our customer board. In our System, we need implement mSGDAM Core to transfer a bundle of 128 descriptors for data moving from cpu to fpga device . I checked " ug_embeded" user guide, but still not clear about " HOW can mSGDMA perfetch IP realize this "。 What's the procedure to implement this ？ Is there an exampel for mSGDMA prefetched enabled design ? We use Linux on CPU 。 Thanks in advance ~Re: mSGDMA mm_Read Data is slow, but mm_Write Data is fast (ok) for "TSE_mSGDMA to HIP AVMM-DMA" logic
Hi @EBERLAZARE_I_Intel ,, I think you're the expert of " mSGDMA IP" area , would you help to double check my original question (or at least relay it to an more suitable person to reply ) ? Thanks very muchWHY is "txs burstcount" missing in Avalon-MM DMA interface w/ PCIe HIP (Arria 10) ?
hi all, we met a performance issue on Arria10 mSGDMA Avalon-MM master(32bit data width) interconnect to PCIE HIP's Avalon-MM (w/ DMA) slave (txs 32bit). For "mSGDMA_writing_to PCIE AVMM(w/ DMA) TXS" operation, data transfer performance is good. But for revere "mSGDMA_reading_from PCIE AVMM(w/ DMA) TXS" direction, data transfer is very slow, we monitored the "txs waitrequest" signal to de-asserted to activate , found found the reading consumes much more clock cycles (16 x) than writing operation. This blocks us for a long time yet. I just compare Avalon-MM interface signals between PCIE HIP's "AVMM ( with DMA)" vs PCIE HIP's "AVMM" variant, then we found the "txs burstcount" signal is missing in PCIE HIP's "AVMM ( with DMA)" interface , while it really exist in PCIE HIP's "AVMM" interface, as following pic: so my question is : waht's the reason of this difference ? Does this "txs burstcount" miss in AVMM-DMA interface would affect the reading (burst) opearion from mSGDMA AValon-MM Master to PCIE HIP TXS (avalon-mm slave) ? Appreciate helps & advices if any. Thanks
