Forum Discussion
Ash_R_Altera
Regular Contributor
2 hours agoHi,
I am referring to the following section of the Arria 10 transceiver PHY UG, https://docs.altera.com/r/docs/683617/21.1/arria-10-transceiver-phy-user-guide/power-up-calibration
As per this, the power-up calibration has a sequence and RX PMA channel calibration almost comes at the end of it. Eventually the rx_cal_busy de-assertion will depends upon the whether the previous blocks i.e. ATX PLL and fPLL calibration are completed or not and whether the PCIe hard IP is enabled or not.
If the PLLs are taking long, check the input reference clocks to it.
Regards