Forum Discussion
New ContributorAgilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation
Regular ContributorHi,
As I understand, this Warning is related to port o_pma_cu_clk of the Reset Sequencer IP. Please check if your connection is as per the documentation recommendation.
The pma_cu_clk must be connected to your IPs.
Please review your code once and let us know if you find something.
Regards
GerhardCadekHi,
yes this is also my understanding. But I do not understand why this Critical Warning occurs. I followed the documentation and the block diagram you sent. There is one o_pma_cu_clk clock generated by every of the two Reset Synchronizer circuits as there is one transceiver bank used on every side (M equals to 1 in the block diagram). The two 25Gbit PCS/PMA transceivers are placed in IO bank 4C driven by one Reset Sequencer instance while the two 10 Gbit PCS/PMA transceivers are placed in IO bank 1C. That design compiled without errors but the Design Assistant reports these Critical Warnings.
Unfortunately my design is currently broken. I generated the Triple-Speed Ethernet MAC PCS/PMA with HPS adapter and connected it the EMAC0 of the HPS in my design. Now quartus fails to synthesize the design. This IP core is generated with an erroneous netlist by Quartus 26.1 (see my post here https://community.altera.com/discussions/ip-and-transceiver/triple-speed-ethernet-ip-for-agilex-5-fails-during-quartus-synthesis/355686 )
Enjoy a great time!
Gerhard
