--- Quote Start ---
Hi, GPK
Yes, I did P&R, but no strange messages turned out. Do you have any other suggestions?
Thanks again.
--- Quote End ---
Hi,
is it possible for you to look deeper into the IP block, in order to find out whether there are parts of the block running ?
BTW: I found this remark in the documentation
RTL Simulation Reports Errors When Using Verilog HDL
EDA RTL simulation started from the Quartus II software reports errors in the
ModelSim® simulator for designs containing Video and Image Processing Suite
MegaCore functions when the output files are in Verilog HDL.
Affected Configurations
This issue affects configurations that use NativeLink to run a ModelSim simulation
from Verilog HDL.
Design Impact
An error message reports that software cannot find the Altera library.
Workaround
Compile the file db/alt_cusp90_package.vhd to the Altera library. To perform this
compilation, modify the top-level .do script in the simulation/modelsim directory.
Solution Status
This issue will be fixed in a future version of the Video and Image Processing Suite.
Kind regards
GPK
Honored Contributor
