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Altera_Forum
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16 years ago

Question about simulation of VIP cores

Hi, I'm doing a simulation of Clocked Video Input with Altera-Modelsim using NativeLink, but it seems the IP cores doesn't respond to my testbench as the attachment below, while I have successfull...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Hi,

to be honest I was not convinced that the reset is the root cause, but you never know ....

In my experience HiZ often means that nothing is connected to the outputs. Do run a complete Quartus P&R. If yes did you some strange messages that something is missing ??? Or have your core tri-state capable outputs ?

Kind regards

GPK

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Hi, GPK

Yes, I did P&R, but no strange messages turned out. Do you have any other suggestions?

Thanks again.