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Hi,
are you using a synchronous reset ? It looks to me that in your testbench the clocks starts after releasing the reset.
Kind regards
GPK
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Hi, GPK
As quoted from the VIP user guide, "The MegaCore function is asynchronously reset when rst is asserted high. The reset must be de-asserted synchronously with respect to the rising edge of the is_clk signal."
And I have commented the delay for the clocks initial as below, but it still doesn't work.
Thanks again!
initial
begin
dclk_in = 0;
//#120;
forever# 25 dclk_in = ~dclk_in;
end
initial
begin
sys_clk = 0;
//#120;
forever# 5 sys_clk = ~sys_clk;
end
Honored Contributor
