Question about simulation of VIP cores

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Hi,

I'm doing a simulation of Clocked Video Input with Altera-Modelsim using NativeLink, but it seems the IP cores doesn't respond to my testbench as the attachment below, while I have successfully simulated the reconfiguration of altera's pll.

My question is that if the VIP cores support simulation or not, are there any differences between simulation of CVI and PLL?

Thanks for reply!

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Hi,

how does your testbench lookslike ?

Kind regards

GPK