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pwiln's avatar
pwiln
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7 years ago

Question about IP : Altera ASMI Parallel IP Core

When performing command Erase a sector :

At the end of command , signal busy is deasserted

Did this mean that the sector erasure has been completed or

I have to check status register bit 0 which means erase in progress and wait til this bit goes low ?

4 Replies

  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi pwiln,

    The busy signal goes high when the ASMI IP core is executing a valid operation (in this case erase operation), and it goes low after the operation completes. Which configuration flash device are you referring to? For EPCS and EPCQ device. you don't require to read the status register. For EPCQL device , you can try to read the status register bit 0 to know if the erase operation is in progress or complete.

    Regards,

    Nooraini

  • pwiln's avatar
    pwiln
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    7 years ago

    Hi Nooraini,

    Configuration flash device used : Micron MT25QL256ABA8SEF IC FLASH Serial NOR 256MBIT Quad I/O ​

    FPGA used : 5AGXMA1D6F31C6N

    So from your answer , I only need to wait for signal BUSY to be deasserted and go to next command ?

    Thanks

    pascal

  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi pwiln,

    If you are using ASMI Parallel IP, you can either just monitor the busy signal goes low (erase operation complete) or use read_status operation to read the status register bit 0. Otherwise to be safe you can use both where once the busy goes low (erase operation complete) wait at least two clock cycle, then execute the read_status operation.

    Regards,

    Nooraini

  • pwiln's avatar
    pwiln
    Icon for New Contributor rankNew Contributor
    7 years ago

    thanks

    we can close the issue.

    pascal​