Honored ContributorHi,
I instantiated a DDR2 core with DDR2 SDRAM Controller v8.0, and enabled the "Memory device DLL enable". The generated DDR2 core has the input port named dqs_delay_ctrl[5..0] and output port named "stratix_dll_control". But in the summary of Analysis & Synthesis, it reported that the total DLLs was 0. Why does it happen? Thanks!
Honored Contributoryou need to instantiate the dll, those ports are for it and should be connected.
That said, i would move to the newer HP DDR core, where this would not be an issue. --dalonHonored ContributorThe "Memory device DLL enable" signal has nothing to do with those ports. That checkbox is to instruct the controller the enable the DLL on the SDRAM chip itself.
The fact that you have those dqs_delay_ctrl ports indicates that you also checked the "Instantiate DLL externally" checkbox in the core. You should only do this if you want manual control over the DQS delay. Edit your core and uncheck the "Instantiate DLL externally" checkbox. JakeHonored ContributorBy the way, leave the "Memory device DLL enable" box checked.
JakeHonored ContributorThank you for your replys.
I have been living without net for a long time.
